Abstract :

— In order to improve computer efficiency, this research investigates the design and synthesis of a 4-phase pipelined Arithmetic Logic Unit (ALU). Through the use of overlapping instruction executions, the pipelined architecture—which includes fetch, decode, execute, and write back phases—increases throughput and decreases latency. In order to meet timing, area, and power limitations, the ALU is designed using one of many Hardware Description Languages (HDL), such Verilog. It is then synthesized into a gate-level representation. The results demonstrate that processing performance and efficiency are considerably enhanced by the 4-phase pipelined ALU. The following terms are used in the index: Arithmetic Logic Unit (ALU), 4-Phase Pipeline, Performance Optimization, Design, Synthesis, and Hardware Description Language (HDL).